Magic is an open source tool originally written by John Ousterhout at UC Berkeley during the 1980s. It is a very flexible layout tool for building and editing layouts for VLSI designs. One might think that Magic is an old layout tool the first time you run it, but in fact, given its open-source license, its simple usage and versatility, Magic is still one of the most popular layout tools in universities and small IC companies. Magic 7.5 is the latest stable version of the tool and is a combined effort of the “Magic Development Team” at http://opencircuitdesign.com/magic
Magic is based on the Mead-Conway “Scalable CMOS” style of design, using lambda for dimensions instead of microns. All foundries specify their process dimensions in microns, while lambda are dimensionless. This means that before sending the data to any foundry, Magic will have to convert its lambda units into microns. This is done in the extraction or building of the .mag file into the .ext file. Magic has different extraction styles for different lambda to microns scale, depending on the process that was chosen. The advantage of working with this lambda rules is that you can have one layout, specify in lambda, and multiple gds files for different process technologies. That’s where the scalable CMOS comes from. The disadvantage of scalable CMOS is that in order to get a valid layout and meet all the design rules of all the processes, each lambda dimension must meet the worst-case design rule requirements for every process intended to be compatible with the technology file. Unless the processes are completely compatible with one another and processes at different feature sizes scale exactly, then the lambda rules cannot ever specify the densest possible widths and spacings of materials.* (Tutorial 1 from Magic)
The easiest way to learn Magic is by doing the tutorials available on its webpage, as well as under the $CAD_HOME/magic/doc/tutorial once it is installed. While doing the tutorials, keep in mind that many of them where written some years ago and some of the macros in there, or bindkeys, are no longer valid and had been updated. To get the latest list of macros, go into your $HOME/lib/magic/sys/.magicrc and you’ll find the complete list of the latest macros within Magic.
Once you read the tutorials, you should be ready to start your own project with Magic. The easiest design to do is a classic inverter. This will be done with the default tech file within Magic, so no -T will be required while running the tool. Open your console and type:
A new window where you’ll draw your layout will pop up, as well as the command interpreter window with some messages about the techfile used and some other warnings.
The first thing you’ll have to do once you have Magic running is to set the layers frame on the right. Go to Options->Toolbar. Now you can select the layers to paint with.
Building the pmos and nmos
First, let’s set the grid:
Then, paint the pdiffusion region for the mos transistor
:box 0 0 5 4
adding the contacts and the poly for the gate
: box 5 0 9 4
: paint pdcont
: box -4 0 0 4
: paint pdcont
: box 1 -2 4 6
: paint poly
Now, it will be easier to move the whole pmos away from the origin so we can build the nmos in there. To do that, place the box around the whole pmos and type “a”. This is another macro for selecting everything within the box surroundings. To move the selection you can use the keypad arrows. It works with Num_Lock on or off.
Repeat the procedure to build the nmos but replace pdiff for ndiff and pdcont for ndcont.
Building the inverter
Both pmos and nmos should be ready in the layout. Align the gate of both devices and put them as close as you can.
Magic has a built-in drc checker, which it will flag as white dots in the region where there is a conflict. The following picture shows the pmos too close from the nmos and the drc error
To see the message behind the drc error, just place the box around the white dots and press “?”. This will write the error message in the comand interpreter window
P-type diffusion must be 10 away from N-type diffusion (MOSIS rule #2.3a)
Once you have the two transistors placed at its minimum spacing, you’ll need to connect the gates together with poly as well as the diffusions to the output metal1.
In order to finish this inverter, we need to put the poly contact, power rails and body contacts to each mos transistor. You can follow the procedure it was described before or you can just use the macros and mouse to do it faster.
Once you are done with it, it should look something like this
There are a couple of important points to notice. First, the area where the poly crosses the diffusion has a diagonally-striped pattern different from both poly and diffusion. This area represents the actual transistor, since FETs are constructed wherever poly passes over diffusion. To see this, place the cursor over the top transistor, and select it by pressing the s key. Now enter :what, which displays the names of the selected paint. Here, the selected area is “ptransistor”; Magic actually changes the paint from pdiffusion to ptransistor when poly crosses over it. The same concept applies when poly crosses over n-diffusion to form an “ntransistor”.
To see which components are connected to a particular rectangle, place the cursor over it and press the s key twice quickly. The first key press selects the rectangle; the second selects everything that’s electrically connected to it. Try this on either metal rail, and notice that they are both electrically isolated from everything else. The top rail must connect to the diffusion on one side of the PFET and the bottom rail to the diffusion on one side of the NFET; otherwise, no current can flow. Thus, we need what’s called a diffusion-to-m1 contact, abbreviated pdc or ndc depending on whether we’re talking about p or n diffusion respectively.
Place the box at ll=(0,5), ur=(4,9) and type :pai ndc. Now make a pdc at ll=(0,19) and ur=(4,27). Checking connectivity shows that the rails are connected to both the adjacent contacts and the diffusion right up to, but not including, the transistor. At this point, check your layout against Figure 4.
To save your layout, type :save. If you want to save it under another name, simply type the name too; e.g., :save newcellname. Magic automatically appends a .mag extension.
The next step is to simulate the layout to verify that it works correctly. Magic’s .mag files are stored simply as a collection of various types of rectangles, but simulators require a netlist of circuit components, such as transistors and capacitors. Recall that a netlist is a list of circuit components and how they’re connected.
You use Magic itself to extract a netlist from a layout. Magic’s extractor recognizes various combinations of rectangles as defined in the tech file and converts them into the appropriate circuit elements. It also extracts connectivity between shapes, thus making a complete netlist.
You must choose an “extraction style”, which tells Magic how to interpret the shapes in the layout. To see the available styles, type :extract style. For our purposes, the important part of the style name is the number, which refers to the minimum transistor length. For example, in the lambda=1.0(scna20_orb) style we’ll use, this length is 2.0mm. This should be the current style; if it’s not, enter:
:extract style lambda=1.0(scna20_orb)
To complete the extraction, simply type :extract. Magic makes an inverter.ext file. This file is an intermediate description of the circuit containing all the information necessary to build a netlist for various simulators. We’re now ready to begin simulation, so quit magic by entering :quit.
Before beginning a simulation, first create a SPICE file and add transistor models and SPICE commands to it. Next, simulate the inverter to verify that it was laid out correctly.
Creating the SPICE File
First, translate the inverter.ext file into something that SPICE can understand. The ext2spice program by Stefanos Sidiropolous that comes with the Magic distribution performs this translation. Simply enter:
ext2spice -f spice3 inverter.ext
We specify “spice3” format output, because earlier SPICE versions can’t handle text strings for labels.
We now have a file that SPICE can understand, but it’s incomplete in an important way. For SPICE to simulate a device correctly, it needs a model, a mathematical description of the device’s behavior. In particular, we now need models for the two transistors (n-type and p-type) that we’ve used in our design.
SPICE has a variety of built-in transistor models specified in terms of sets of parameters. These parameters vary according to the fabrication process used, so it’s up to the user to specify the correct parameters for the process being used. Fortunately, you don’t have to figure these out yourselves—you can get them from MOSIS at ftp://ftp.mosis.edu/pub/mosis/vendors/orbit-scna20. This FTP site contains a whole slew of data from past runs; we chose a typical one from the “Level 2 Parameters” section. One minor detail—note that you need to change the “CMOSN” and “CMOSP” to match ext2spice’s output, “NFET” and “PFET”.