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OpenSource IC design flow

I’ve been working with commercial tools for IC design for the last 5 years so far, and I’ve also started to get my hands in the open source tools available out there. The reason behind this is that for any startup or small company, to get a commercial ASIC tool is one, or maybe the only one, higher expense. I’m mean, for sure you can get cheaper commercial tools, not just one of the two main companies, I’m talking of course about Cadence and Mentor. But even the most accessible commercial tools are still expensive for a small company or a startup. Let’s say you are still in collage, and you have an idea for an IC that you’d like to develop. How would you proceed to reach that goal? you have to first get the tool running, then get the part to the Fab, if you are in a university most probably you’ll do it through Mosis. Then, once your part is back, you still need to test it and get some measurements, and once you have all that you already should have your customer, and let’s hope you did everything right in the first silicon, otherwise you’ll have to pay for an extra set of masks to fix your first part.

What I’m trying to say here is that getting the right IC design tools is just the first step to get your part done. And deciding which tool you’ll use it will be as critical as when you are doing your design.

So far, in the open source community there has been some attempts to get a complete open source ic design flow, Electric and the set of tools in Fedora Labs are two of them. Talking a little bit about each of them, I have to say that I haven’t tried Electric yet, but one thing that I love is the way it is documented. I mean, Prof. Baker uses it in his courses, and he has many videos with really good tutorials about it. For what I saw in those videos, Electric is a really good schematic capturer but it doesn’t have an open source simulation embedded in it. They use LTspice instead, which is a freeware.

Fedora Labs, in my opinion, it is more focus on tools to do digital synthesis designs, not so much analog IC design. Which if your application is using VHDL and synthesis, then that might be a good starting point.

Going forward, as for analog IC design there isn’t much in the open source community (Electric would be one)  I’m trying to get here some tools to make this possible. Magic is a good one for layout, although I am finding it a little bit complicated to use with hierarchical cells, maybe is because I am not using it right :-/ , and it doesn’t have what the commercial tools have which is the components related to the sch associated to the layout you are working on. That feature, is one that I haven’t found in any of the layout tools I’ve been using so far.

In any case, this is what I’m trying to do, get a good and easy to follow open source design flow. This is not an easy task, as there are many features that the commercial tools have that the open sources tools don’t have.


Free Model Foundry

While browsing the web, I came across this site about open source simulation models for system level verification. Apparently they are in the business since 1995, and the last news article is from 2009.

We haven’t reached in our flow the system level yet, but it is good to have this for future reference.

New Magic Tutorial post

I’ve just updated a new magic tutorial post under the Layout VLSI pages. Take a look at it


Welcome to Open Source IC Design Blog.

In this blog you will find our experience in using open source tools to get a VLSI chip all the way from design, simulation, layout and testing.

Please, feel free to comment.